The present disclosure relates to a voltage regulator circuit. In recent years, there have been increasingly strong demands to shorten the rise time of the output voltage of voltage regulator circuits. In response to such demands, in a voltage regulator circuit disclosed in Japanese Unexamined Patent Application Publication No. 2010-140254 for example, the gate voltage of an output MOS transistor is controlled when the voltage regulator circuit is initiated so that the output voltage comes to be within a prescribed voltage range in a short time. Specifically, a voltage generated through voltage division using two capacitance elements is supplied to the gate of the output MOS transistor.
In the voltage regulator circuit disclosed in Japanese Unexamined Patent Application Publication No. 2010-140254, there is a possibility that an overshoot will occur when the output voltage rises in the case where there is a difference between the voltage supplied to the gate of the output MOS transistor at the time when the voltage regulator circuit is initiated and the voltage supplied at the time when the output voltage has reached a target level. Therefore, variations in characteristics caused by such an overshoot are an issue even through the rise speed is improved.